1. Field of the Invention
This invention relates an input buffer in semiconductors, and more particularly to an input buffer which can reduce power consumption by decreasing a variation of an operation bias voltage.
2. Description of the Prior Art
FIG. 1 is a conventional input circuit diagram used in a high speed interface according to the prior art.
In case that an input buffer circuit illustrated in FIG. 1 is used as a Stup Series Terminated Tranciever Logic (SSTTL) interface, a reference voltage Vref is 1.485 volts, while 1.685 or 1.285 volts is supplied to an input terminal Vin. At this time, if a clock enable signal Cken is at a logic "high" level, direct current flows from Vdd power supply terminal to Vss ground terminal since overall transistors of the input buffer are turned on. However, there is a high voltage difference between Vdd and Vss, and this causes a lot of DC to flow in the input circuit, thereby increasing the power consumption.
In particular, the more pins a memory device has (e.g., 8 MB SGRAM has 53 pins in the input buffer), the more the power consumption caused by flowing current in the input buffer will be increased.
As described above, the conventional input buffer has a disadvantage that a wide variation of the bias voltage causes a lot of DC to flow from the power supply terminal to the ground terminal. As a result, the power consumption may be increased.